Working Student - SV-UVM based Verification for Gate-Driver ICs (f/m/div)

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Your role Key responsibilities in your new role Shape the future: You design and implement comprehensive testmode verification scenarios and test sequences to validate testmode functionality Take responsibility: You extend UVM-based scoreboards with testmode-specific checkers and validation logic to identify functional discrepancies and timing violations Focus on the future: You establish, optimize, and maintain a scalable testmode regression suite for continuous validation, silicon characterization, and future derivative products Keep track of everything: You analyze simulation results, monitor verification coverage, and ensure test completeness across different testmode configurations Work Reliably: You perform waveform analysis and support root-cause investigations to resolve verification issues efficiently Keep your colleagues informed: You create clear verification reports, test methodology documentation,