Working Student / Internship – RTL Design & SPICE Simulation Automation (f/m/div)

Shape the future: Develop expandable, parameterizable RTL in Verilog or VHDL to support various experiments and configurations Reliable work: Create and maintain simulation-ready test structures and interfaces as needed Identify needs: Set up and execute SPICE analyses (e.g., transient, DC, AC—depending on the experiment) and evaluate results Take responsibility: Build an automated SPICE simulation flow, including scripted run setup (batch runs, parameter sweeps), result extraction & post-processing and generation of reproducible reports/artifacts Data is everything: Document the workflow clearly (how to run, how to extend, assumptions, directory structure) Keep the overview: Write supporting scripts in Python and/or Tcl (tool integration, parsing, automation) Study Field: Currently enrolled student (Bachelor's (Preferred) / Master's) in Electrical Engineering Skills: Solid fundamentals in digital design (combinational/sequential logic, FSMs, timing basics); ability to write clean RTL in Verilog or VHDL (modular, readable, maintainable), fundamentals of CMOS circuits (basic gates, switching behavior, delay/power concepts) and familiarity with Linux command line tools and Git versio