Senior Staff Engineer Digital Verification (f/m/div)

Create and define verification plans for digital or digital mixed signal designs Create new and improve existing verification environments in SystemVerilog/UVM Write and execute tests for RTL and gate-level Debug issues in design and verification environments Lead and coordinate other verification engineers in your projects Closely cooperate with architects, designers and other verification engineers Mentoring of junior colleagues, consultants and students Contribute to enhancement of existing methodologies and flows University degree in Electrical Engineering, Information Technology, Telematics, or a related field with a focus on electronics At least 6 years of professional experience in digital verification; experience in technical leadership is highly desirable Expert knowledge of SystemVerilog and UVM and solid understanding of SystemVerilog for design Strong scripting skills using technologies such as bash, tcsh, Python, TCL or similar Knowledge of formal verification and mixed signal verification is an advantage Fluent English language skills with German skills as a plus We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for ev